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ds05-11404-2e fujitsu semiconductor data sheet memory mobile fcram tm cmos 16 mbit (1 m word 16 bit) mobile phone application specific memory mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll cmos 1,048,576-word 16 bit fast cycle random access memory with low power sram interface n n n n description the fujitsu mb82d01171a is a cmos fast cycle random access memory (fcram) with asynchronous static random access memory (sram) interface containing 16,777,216 storages accessible in a 16-bit format. this mb82d01171a is suited for low power applications such as cellular handset and pda. note: fcram is a trademark of fujitsu limited, japan. n n n n product lineup n n n n packages parameter mb82d01171a 80 80l 80ll 85 85l 85ll 90 90l 90ll access time (t aa max, t ce max) 80 ns 85 ns 90 ns active current (i dda1 max) 20 ma standby current (i dds1 max) 200 m a 100 m a70 m a 200 m a100 m a 70 m a 200 m a 100 m a 70 m a power down current (i ddp max) 10 m a 48-ball plastic fbga 48-ball plastic fbga (bga-48p-m16) (bga-48p-m18)
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 2 n n n n features ? asynchronous sram interface ?1 m word 16 bit organization ? fast random cycle time : t rc = 90 ns ? fast random access time : t aa = t ce = 80 ns, 85 ns, 90 ns ? low power consumption : i dds1 = 200 m a, 100 m a (l version) , 70 m a (ll version) ? wide operating conditions : v dd = + 2.3 v to + 2.7 v + 2.7 v to + 3.1 v + 3.1 v to + 3.5 v t a = - 30 c to + 85 c ? byte write control ? 4 words address access capability ? power down control by ce2
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 3 n n n n pin assignments n n n n pin description pin name description a 0 to a 19 address input ce 1 chip enable (low active) ce2 chip enable (high active) we write enable (low active) oe output enable (low active) lb lower byte write control (low active) ub upper byte write control (low active) dq 1 to dq 8 lower byte data input/output dq 9 to dq 16 upper byte data input/output v dd power supply v ss ground nc no connection a b c d e f g h a 4 a 3 a 2 a 1 a 0 ce1 oe v ss a 17 a 7 a 6 a 5 dq 1 dq 9 dq 10 dq 2 ub lb a 18 nc dq 3 dq 11 dq 12 dq 4 ce2 we nc a 19 dq 6 dq 13 v dd dq 5 a 8 a 9 a 10 a 11 dq 8 dq 15 dq 14 dq 7 a 12 a 13 a 14 a 15 a 16 nc dq 16 v ss 16 5 4 3 2 a b c d e f g h lb dq 9 dq 10 v ss v dd dq 15 dq 16 a 18 oe ub dq 11 dq 12 dq 13 dq 14 a 19 a 8 a 0 a 3 a 5 a 17 nc a 14 a 12 a 9 a 1 a 4 a 6 a 7 a 16 a 15 a 13 a 10 a 2 ce1 dq 2 dq 4 dq 5 dq 6 we a 11 ce2 dq 1 dq 3 v dd v ss dq 7 dq 8 nc 16 5 4 3 2 (top view) flash compatible fbga (suffix pbt) sram compatible fbga (suffix pbn) (bga-48p-m16) (bga-48p-m18)
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 4 n n n n block diagram v dd v ss ce2 ce1 we lb ub oe a 0 to a 19 dq 1 to dq 8 dq 9 to dq 16 address latch & buffer row decoder memory cell array 16,777,216 bit i/o buffer input data latch & control sense / switch output data control column / decoder address latch & buffer power control timing control
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 5 n n n n function truth table * 1 *1 : v = valid, l = logic low, h = logic high, x = either l or h, high-z = high impedance *2 : power down mode can be entered from standby state and all dq pins are in high-z state. *3 : output disable mode should not be kept longer than 1 m s. *4 : byte control at read mode is not supported. mode ce 1ce2 we oe lb ub dq 1 to dq 8 dq 9 to dq 16 i dd data retention power down * 2 xlxxxxhigh-zhigh-zi ddp no standby (deselect) h h xxxxhigh-zhigh-zi dds yes output disable* 3 l h h x x high-z high-z i dda read* 4 lxx output valid output valid write lh ll input valid input valid write (lower byte) l h input valid invalid write (upper byte) h l invalid input valid
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 6 n n n n absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions *1 : all voltages are referenced to v ss . *2 : minimum dc voltage on input or i/o pins are - 0.3 v. during voltage transitions, inputs may undershoot v ss to - 1.0 v for periods of up to 5 ns. maximum dc voltage on input and i/o pins are v dd + 0.3 v. during voltage transitions, inputs may positive overshoot to v dd + 1.0 v for periods of up to 5 ns. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max voltage of v dd supply relative to v ss v dd - 0.5 + 3.6 v voltage at any pin relative to v ss v in - 0.5 + 3.6 v v out - 0.5 + 3.6 v short circuit output current i out - 50 + 50 ma storage temperature t stg - 55 + 125 c parameter symbol value unit min max supply voltage * 1 v dd ( 31 ) 3.1 3.5 v v dd ( 27 ) 2.7 3.1 v v dd ( 23 ) 2.3 2.7 v v ss 00v high level input voltage * 1, * 2 v ih ( 31 ) 2.6 v dd + 0.3 and 3.6 v v ih ( 27 ) 2.2 v dd + 0.3 v v ih ( 23 ) 2.0 v dd + 0.3 v low level input voltage * 1, * 2 v il ( 31 ) - 0.3 0.5 v v il ( 27 ) - 0.3 0.5 v v il ( 23 ) - 0.3 0.4 v ambient temperature t a - 30 85 c
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 7 n n n n pin capacitance (f = 1.0 mhz, t a = + 25 c) n n n n electrical characteristics 1. dc characteristics (continued) parameter symbol conditions value unit min typ max address input capacitance c in1 v in = 0 v ?? 5pf control input capacitance c in2 v in = 0 v ?? 5pf data input/output capacitance c io v io = 0 v ?? 8pf parameter symbol conditions value unit min max input leakage current i li v ss v in v dd - 1.0 + 1.0 m a output leakage current i lo 0 v v out v dd , output disable - 1.0 + 1.0 m a output high voltage level v oh(31) v dd = v dd(31) , i oh = - 0.5 ma 2.4 ? v v oh(27) v dd = v dd(27) , i oh = - 0.5 ma 2.25 ? v v oh(23) v dd = v dd(23) , i oh = - 0.5 ma 1.8 ? v output low voltage level v ol i ol = 1 ma ? 0.4 v v dd power down current i ddp v dd = v dd(31) max, v in = v ih or v il , ce2 0.2 v ? 20 m a v dd = v dd(27, 23) max, v in = v ih or v il , ce2 0.2 v ? 10 m a v dd standby current i dds v dd = v dd(31) max, v in = v ih or v il ce 1 = ce2 = v ih , i out = 0 ma ? 5.5 ma l version ? 2.0 ll version ? 1.5 i dds v dd = v dd(27, 23) max, v in = v ih or v il ce 1 = ce2 = v ih , i out = 0 ma ? 5 ma l version ? 1.5 ll version ? 1 i dds1 v dd = v dd(31) max, v in 0.2 v or v in 3 v dd - 0.2 v, ce 1 = ce2 3 v dd - 0.2 v, i out = 0 ma ? 250 m a l version ? 150 ll version ? 120 i dds1 v dd = v dd(27, 23) max, v in 0.2 v or v in 3 v dd - 0.2 v, ce 1 = ce2 3 v dd - 0.2 v, i out = 0 ma ? 200 m a l version ? 100 ll version ? 70
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 8 (continued) notes: all voltages are referenced to vss. dc characteristics are measured after following power-up timing. i out depends on the output load conditions. parameter symbol conditions value unit min max v dd active current i dda1 v dd(31) = v dd max, v in = v ih or v il , ce 1 = v il and ce2 = v ih , i out = 0 ma t rc / t wc = min ? 25 ma v dd(27, 23) = v dd max, v in = v ih or v il , ce 1 = v il and ce2 = v ih , i out = 0 ma 20 i dda2 v dd(31) = v dd max, v in = v ih or v il , ce 1 = v il and ce2 = v ih , i out = 0 ma t rc / t wc = 1 m s ? 4.0 ma v dd(27, 23) = v dd max, v in = v ih or v il , ce 1 = v il and ce2 = v ih , i out = 0 ma 3.0
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 9 2. ac characteristics (1) read operation *1: the output load is 30 pf. *2: the output load is 5 pf. *3: the t ce is applicable if oe is brought to low before ce 1 goes low and is also applicable if actual value of both or either t aso or t clol is shorter than specified value. *4: applicable only to a 0 and a 1 when both ce 1 and oe are kept at low for the address access. *5: applicable if oe is brought to low before ce 1 goes low. *6: the t aso , t clol (min) and t op (min) are reference values when the access time is determined by t oe . if actual value of each parameter is shorter than specified minimum value, t oe become longer by the amount of subtraction actual value from specified minimum value. for example, if actual t aso , t aso (actual) , is shorter than specified minimum value, t aso (min) , during oe control access (i.e., ce 1 stays low) , the t oe become t oe (max) + t aso (min) - t aso (actual) . *7: the t aso[abs] and t op[abs] is the absolute minimum value during oe control access. *8: if actual value of either t clol or t op is shorter than specified minimum value, both t olah and t olch become t rc (min) - t clol (actual) or t rc (min) - t op (actual) . *9: maximum value is applicable if ce 1 is kept at low. parameter symbol -80/-80l/ -80ll -85/-85l/ -85ll -90/-90l/ -90ll unit notes minmaxminmaxminmax read cycle time t rc 90 ? 90 ? 90 ? ns chip enable access time t ce ? 80 ? 85 ? 90 ns *1, *3 output enable access time t oe ? 45 ? 45 ? 45 ns *1 address access time t aa ? 80 ? 85 ? 90 ns *1, *4 output data hold time t oh 5 ? 5 ? 5 ? ns *1 ce 1 low to output low-z t clz 5 ? 5 ? 5 ? ns *2 oe low to output low-z t olz 0 ? 0 ? 0 ? ns *2 ce 1 high to output high-z t chz ? 30 ? 30 ? 30 ns *2 oe high to output high-z t ohz ? 25 ? 25 ? 25 ns *2 address setup time to ce 1 low t asc - 5 ?- 5 ?- 5 ? ns *5 address setup time to oe low t aso 45 ? 45 ? 45 ? ns *3, *6 t aso[abs] 10 ? 10 ? 10 ? ns *7 address invalid time t ax ? 5 ? 5 ? 5ns *4 ce 1 low to address hold time t clah 90 ? 90 ? 90 ? ns *4 oe low to address hold time t olah 45 ? 45 ? 45 ? ns *4, *8 ce 1 high to address hold time t chah - 5 ?- 5 ?- 5 ? ns oe high to address hold time t ohah - 5 ?- 5 ?- 5 ? ns ce 1 low to oe low delay time t clol 45 1000 45 1000 45 1000 ns *3, *6, *8, *9 oe low to ce 1 high delay time t olch 45 ? 45 ? 45 ? ns *8 ce 1 high pulse width t cp 20 ? 20 ? 20 ? ns oe high pulse width t op 45 1000 45 1000 45 1000 ns *6, *8, *9 t op[abs] 20 ? 20 ? 20 ? ns *7
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 10 (2) write operation *1: minimum value must be equal or greater than the sum of actual t cw (or t wp ) and t wrc (or t wr ) . *2: new write address is valid from either ce 1 or we is brought to high. *3: maximum value is applicable if ce 1 is kept at low and both we and oe are kept at high. *4: the t oeh is specified from end of t wc (min) and is a reference value when access time is determined by t oe . if actual value is shorter than specified minimum value, t oe become longer by the amount of subtracting actual value from specified minimum value. *5: the t oeh[abs] is the absolute minimum value if write cycle is terminated by we and ce 1 stays low. *6: t ohcl (min) must be satisfied if read operation is not performed prior to write operation. in case oe is disabled after t ohcl (min) , we low must be asserted after t rc (min) from ce 1 low. in other words, read operation is initiated if t ohcl (min) is not satisfied. *7: applicable if ce 1 stays low after read operation. *8: t cw and t wp is applicable if write operation is initiated by ce 1 and we , respectively. *9: t wrc and t wr is applicable if write operation is terminated by ce 1 and we , respectively. the t wr (min) can be ignored if ce 1 is brought to high together or after we is brought to high. in such case, the t cp (min) must be satisfied. parameter symbol -80/-80l/ -80ll -85/-85l/ -85ll -90/-90l/ -90ll unit notes min max min max min max write cycle time t wc 90 ? 90 ? 90 ? ns *1 address setup time t as 0 ? 0 ? 0 ? ns *2 address hold time t ah 45 ? 45 ? 45 ? ns *2 ce 1 write setup time t cs 0 1000 0 1000 0 1000 ns ce 1 write hold time t ch 0 1000 0 1000 0 1000 ns we setup time t ws 0 ? 0 ? 0 ? ns we hold time t wh 0 ? 0 ? 0 ? ns lb and ub setup time t bs - 5 ?- 5 ?- 5 ? ns lb and ub hold time t bh - 5 ?- 5 ?- 5 ? ns oe setup time t oes 0 1000 0 1000 0 1000 ns *3 oe hold time t oeh 45 1000 45 1000 45 1000 ns *3, *4 t oeh[abs] 20 ? 20 ? 20 ? ns *5 oe high to ce 1 low setup time t ohcl - 3 ?- 3 ?- 3 ? ns *6 address hold time to oe high t ohah 0 ? 0 ? 0 ? ns *7 ce 1 write pulse width t cw 60 ? 60 ? 60 ? ns *1, *8 we write pulse width t wp 60 ? 60 ? 60 ? ns *1, *8 ce 1 write recovery time t wrc 15 ? 15 ? 15 ? ns *1, *9 we write recovery time t wr 15 1000 15 1000 15 1000 ns *1, *3, *9 data setup time t ds 20 ? 20 ? 20 ? ns data hold time t dh 0 ? 0 ? 0 ? ns ce 1 high pulse width t cp 20 ? 20 ? 20 ? ns *9
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 11 (3) power down parameters (4) other timing parameters *1: it may write some data into any address location if t chwx is not satisfied. *2: must satisfy t chh (min) after t c2lh (min) . *3: requires power down mode entry and exit after t c2hl . *4: the input transition time (t t ) at ac testing is 5 ns as shown in below. if actual t t is longer than 5 ns, it may violate some timing parameters of ac specification. (5) ac test conditions parameter symbol value unit note min max ce2 low setup time for power down entry t csp 10 ? ns ce2 low hold time after power down entry t c2lp 100 ? ns ce 1 high hold time following ce2 high after power down exit t chh 350 ?m s ce 1 high setup time following ce2 high after power down exit t chs 10 ? ns parameter symbol value unit note min max ce 1 high to oe invalid time for standby entry t chox 20 ? ns ce 1 high to we invalid time for standby entry t chwx 20 ? ns *1 ce2 low hold time after power-up t c2lh 50 ?m s*2 ce2 high hold time after power-up t c2hl 50 ?m s*3 ce 1 high hold time following ce2 high after power-up t chh 350 ?m s*2 input transition time t t 125ns*4 parameter symbol conditions measured value unit note input high level v ih v dd = 3.1 v to 3.5 v 2.6 v v dd = 2.7 v to 3.1 v 2.3 v v dd = 2.3 v to 2.7 v 2.0 v input low level v il v dd = 3.1 v to 3.5 v 0.5 v v dd = 2.7 v to 3.1 v 0.5 v v dd = 2.3 v to 2.7 v 0.4 v input timing measurement level v ref v dd = 3.1 v to 3.5 v 1.5 v v dd = 2.7 v to 3.1 v 1.3 v v dd = 2.3 v to 2.7 v 1.1 v input transition time t t between v il and v ih 5ns
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 12 n n n n timing diagram 1. read timing #1 (oe control access) 2. read timing #2 (ce 1 control access) ce1 address oe dq (output) t rc t ce t oe t op t oe t olch t ohz t clol t aso t olz t oh t ohz t olz t oh t rc t ohah t aso t ohah a ddress valid a ddress valid valid data output valid data output note : ce2 and we must be high for entire read cycle. ce1 address oe dq (output) t rc t ce t asc t oe t olch t cp t chz t ce t chz t clz t oh t clz t oh t rc t chah t asc t chah address valid address valid valid data output valid data output note : ce2 and we must be high for entire read cycle.
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 13 3. read timing #3 (address access after oe control access) 4. read timing #4 (address access after ce 1 control access) ce1 address (a 19 - a 2 ) address (a 1 , a 0 ) oe dq (output) t rc t rc t aso t olah t oe t ohz t olz t oh t oh t ohah t aa t ax address valid address valid valid data output valid data output address valid (no change) address valid note : ce2 and we must be high for entire read cycle. ce1 address (a 19 -a 2 ) address (a 1 , a 0 ) oe dq (output) t rc t rc t asc t clah t ce t chz t clz t oh t oh t chah t aa t ax address valid address valid valid data output valid data output address valid (no change) address valid note : ce2 and we must be high for entire read cycle.
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 14 5. write timing #1 (ce 1 control) ce1 address we dq (input) ub , lb oe t wc t ws t as t ah t as t cw t wrc t wh t ws t bh t bs t bs t ohcl t ds t dh address valid valid data input note : ce2 must be high for write cycle.
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 15 6. write timing #2-1 (we control, single write operation) ce1 address we dq (input) ub , lb oe t wc t cs t ohcl t as t ohah t ah t as t cp t ch t wp t wr t bh t bs t oes t ds t ohz t dh address valid valid data input note : ce2 must be high for write cycle.
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 16 7. write timing #2 (we control, continuous write operation) ce1 address we dq (input) ub , lb oe t wc t cs t ohcl t as t ohah t ah t as t wp t wr t bh t bs t bs t oes t ds t ohz t dh address valid valid data input
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 17 8. read/write timing #1-1 (ce 1 control) ce1 address we dq ub , lb oe t wc t ws t wh t cp t as t chah t ah t asc t cw t wrc t wh t ws t bh t bs t ohcl t ds t chz t oh t dh t clz t olz t clol read data output write data input write address read address note : write address is valid from either ce 1 or we of last falling edge.
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 18 9. read/write timing #1-2 (ce 1 control) ce1 address we dq ub , lb oe t rc t ws t wh t wrc ( min ) t asc t wrc t chah t as t cp t wh t ws t bs t bh t ce t oeh t dh t clz t oh t chz t ohcl read address write address write data input read data output note : the t oeh is specified from the time satisfied both t wrc and t wr (min) .
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 19 10. read (oe control) /write (we control) timing #2-1 ce1 address read data output write data input we dq ub , lb oe t wc t wp t as t ah t ohah t aso t wr t bh t bs t oes t oh t ohz t ds t dh t olz t oeh low write address read address note : ce 1 can be tied to low for we and oe controlled operation. when ce 1 is tied to low, output is exclusively controlled by oe .
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 20 11. read (oe control) /write (we control) timing #2-2 ce1 address read address valid read data output write data input write address we dq ub , lb oe t rc t aso t as t ohah t bs t bh t wr t oeh t oe t olz t dh t ohz t oh t oes low note : ce 1 can be tied to low for we and oe controlled operation. when ce 1 is tied to low, output is exclusively controlled by oe .
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 21 12. power down timing 13. standby entry timing after read or write 14. power-up timing 1 t chs t chh t c2lp t csp power down entry power down mode power down exit high-z ce1 ce2 dq t chox t chwx active ( read ) standby active ( write ) standby ce1 oe we note : both t chox and t chwx define the earliest entry timing for standby mode. if either of timing is not satisfied, it takes t rc (min) period from either last address transition of a 0 and a 1 , or ce 1 low to high transition. t chh t c2lh t chs v dd min 0 v ce1 ce2 v dd note : it is recommended to keep ce2 at low during v dd power-up. the t c2lh specifies after v dd reaches specified minimum level.
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 22 15. power-up timing 2 t chh t c2hl t csp v dd min 0 v ce1 ce2 v dd t chs t c2lp t c2hl note : the t c2hl specifies from ce2 low to high transition after v dd reaches specified minimum level. ce1 must be brought to high prior to or together with ce2 low to high transition.
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 23 n n n n data retention 1. low v dd characteristics 2. data retention timing parameter symbol test conditions value unit min max v dd data retention supply voltage v dr ce 1 = ce2 3 v dd - 0.2 v or, ce 1 = ce2 = v ih , 2.1 3.5 v v dd data retention supply current i dr v dd = v dd ( 23 ) , v in = v ih ( 23 ) or v il ce 1 = ce2 = v ih ( 23 ) , i out = 0 ma ? 5 ma l version ? 1.5 ll version ? 1 i dr1 v dd = v dd ( 23 ) , v in 0.2 v or v in 3 v dd - 0.2 v, ce 1 = ce2 3 v dd - 0.2 v, i out = 0 ma ? 200 m a l version ? 100 ll version ? 70 data retention setup time t drs v dd = v dd ( 27 ) at data retention entry 0 ? ns data retention recovery time t drr v dd = v dd ( 27 ) after data retention 90 ? ns v dd voltage transition time d v/ d t ? 0.5 ? v/ m s 3.5 v v dd t drs ce1 = ce2 3 v dd - 0.2 v or v ih (23) min t drr d v/ d t d v/ d t ce2 ce1 2.7 v 2.1 v 0.4 v v ss data retention mode data bus must be in high-z at data retention entry.
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 24 n n n n ordering information part number package remarks mb82d01171a-80pbt 48-ball plastic fbga 0.8 mm pitch (bga-48p-m16) t ce = 80 ns max, i dds1 = 200 m a max flash compatible package MB82D01171A-80Lpbt 48-ball plastic fbga 0.8 mm pitch (bga-48p-m16) t ce = 80 ns max, i dds1 = 100 m a max flash compatible package MB82D01171A-80Llpbt 48-ball plastic fbga 0.8 mm pitch (bga-48p-m16) t ce = 80 ns max, i dds1 = 70 m a max flash compatible package mb82d01171a-85pbt 48-ball plastic fbga 0.8 mm pitch (bga-48p-m16) t ce = 85 ns max, i dds1 = 200 m a max flash compatible package mb82d01171a-85lpbt 48-ball plastic fbga 0.8 mm pitch (bga-48p-m16) t ce = 85 ns max, i dds1 = 100 m a max flash compatible package mb82d01171a-85llpbt 48-ball plastic fbga 0.8 mm pitch (bga-48p-m16) t ce = 85 ns max, i dds1 = 70 m a max flash compatible package mb82d01171a-90pbt 48-ball plastic fbga 0.8 mm pitch (bga-48p-m16) t ce = 90 ns max, i dds1 = 200 m a max flash compatible package mb82d01171a-90lpbt 48-ball plastic fbga 0.8 mm pitch (bga-48p-m16) t ce = 90 ns max, i dds1 = 100 m a max flash compatible package mb82d01171a-90llpbt 48-ball plastic fbga 0.8 mm pitch (bga-48p-m16) t ce = 90 ns max, i dds1 = 70 m a max flash compatible package mb82d01171a-80pbn 48-ball plastic fbga 0.75 mm pitch (bga-48p-m18) t ce = 80 ns max, i dds1 = 200 m a max sram compatible package MB82D01171A-80Lpbn 48-ball plastic fbga 0.75 mm pitch (bga-48p-m18) t ce = 80 ns max, i dds1 = 100 m a max sram compatible package MB82D01171A-80Llpbn 48-ball plastic fbga 0.75 mm pitch (bga-48p-m18) t ce = 80 ns max, i dds1 = 70 m a max sram compatible package mb82d01171a-85pbn 48-ball plastic fbga 0.75 mm pitch (bga-48p-m18) t ce = 85 ns max, i dds1 = 200 m a max sram compatible package mb82d01171a-85lpbn 48-ball plastic fbga 0.75 mm pitch (bga-48p-m18) t ce = 85 ns max, i dds1 = 100 m a max sram compatible package mb82d01171a-85llpbn 48-ball plastic fbga 0.75 mm pitch (bga-48p-m18) t ce = 85 ns max, i dds1 = 70 m a max sram compatible package mb82d01171a-90pbn 48-ball plastic fbga 0.75 mm pitch (bga-48p-m18) t ce = 90 ns max, i dds1 = 200 m a max sram compatible package mb82d01171a-90lpbn 48-ball plastic fbga 0.75 mm pitch (bga-48p-m18) t ce = 90 ns max, i dds1 = 100 m a max sram compatible package mb82d01171a-90llpbn 48-ball plastic fbga 0.75 mm pitch (bga-48p-m18) t ce = 90 ns max, i dds1 = 70 m a max sram compatible package
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 25 n n n n package dimensions (continued) 48-ball plastic fbga (bga-48p-m16) dimensions in mm (inches) c 2000 fujitsu limited b48016s-1c-1 9.00?.10(.354?004) 6.00?.10 (.236?004) 0.36?.10 (.014?004) .041 ?004 +.006 ?.10 +0.15 1.05 index area (mounting height) (stand off) 0.10(.004) 0.20(.008) s s (5.60(.220)) (4.00(.157)) 0.80(.031) typ 0.80(.031) typ 6 5 4 3 2 1 hgf edcba 48-0.45?.10 (48-.018?004) m 0.08(.003)
mb82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll 26 (continued) 48-ball plastic fbga (bga-48p-m18) dimensions in mm (inches) c 2001 fujitsu limited b48018s-c-1-1 9.00 0.10(.354 .004) 6.00 0.10 (.236 .004) 0.25 0.10 (.010 .004) .041 C .004 +.006 C 0.10 +0.15 1.05 index area (mounting height) (stand off) 0.10(.004) 0.20(.008) s s (5.25(.207)) (3.75(.148)) 0.75(.030) typ 0.75(.030) typ 6 5 4 3 2 1 h g fedcb 48-?0.35 0.10 (48-?.014 .004) m 0.08(.003) s a index mark
mb 82d01171a -80/80l/80ll/85/85l/85ll/90/90l/90ll fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f 0112 ? fujitsu limited printed in japan

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